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  <h1><span class="strip">ModelSim</span> Coverage Summary</h1>
  <h3>Design Unit: work.tb_usb_rcvr(test)</h3>
  <hr/><h3>Design Unit Coverage Details:</h3>
  <table cellspacing="2" cellpadding="2"><tr><td class="odd" colspan="4">Weighted Average:</td><td class="bgGreen">99.01%</td></tr>
  <tr><th class="odd" align="left">Coverage Type</th><th class="even">Bins</th><th class="odd">Hits</th><th class="odd">Misses</th><th class="even">Coverage (%)</th></tr>
  <tr><td class="odd"><a href="s000002.htm#27">Statement</a></td><td class="even_r">121</td><td class="odd_r">121</td><td class="odd_r">0</td><td class="bgGreen">100.00%</td></tr>
<tr><td class="odd"><a href="t000002.htm">Toggle</a></td><td class="even_r">34</td><td class="odd_r">33</td><td class="odd_r">1</td><td class="bgGreen">97.05%</td></tr>
<tr><td class="odd"><a href="a000002.htm">Assertion Attempted</a></td><td class="even_r">1</td><td class="odd_r">1</td><td class="odd_r">0</td><td class="bgGreen">100.00%</td></tr>
<tr><td class="odd"><a href="a000002.htm">Assertion Failures</a></td><td class="even_r">1</td><td class="odd_r">0</td><td class="odd_r">-</td><td class="bgGreen">0.00%</td></tr>
<tr><td class="odd"><a href="a000002.htm">Assertion Successes</a></td><td class="even_r">1</td><td class="odd_r">1</td><td class="odd_r">0</td><td class="bgGreen">100.00%</td></tr>
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  <hr/><h3>Scope Details:</h3>
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  <dt><b>Design Unit Name:</b></dt><dd>work.tb_usb_rcvr(test)</dd>
  <dt><b>Language:</b></dt><dd>VHDL</dd>
  <dt><b>Source File:</b></dt><dd><a href="__source_tb__usb__rcvr.vhd.htm#18">source/tb_usb_rcvr.vhd</a></dd>
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